School of Engineering and Technology, (SET)
AT81.06 : VLSI Design  3(2-3)
Course Objectives:

This course focuses on the design and synthesis of Very Large Scale Integrated (VLSI) chips using CMOS technology focusing towards the development of an Application Specific Integrated Circuit (ASIC) for complex digital systems using integrated circuit cells as building blocks and employing top-down design methods. ASIC design issues at layout, schematic, logic and RTL levels will be studied. Commercial design software will be used for laboratory exercises. An overview of hardware description languages (HDL) and VLSI computer-aided design (CAD) tools and theoretical concepts in VLSI architectures and algorithms will also be discussed. This is a project-oriented course in which the students will be designing and evaluating digital circuits.

Learning Outcomes:
The students on the completion of this course would be able to:
•         Carry out HDL design, logic design, layout design and simulation and testing for VLSI applications
•         Solve VLSI design problems using appropriate tools
•         Design and develop an FPGA based applications
Pre-requisite(s):

None
Course Outline:
I.          Introduction to VLSI
1.    Digital systems and VLSI
2.    Gate Arrays
3.    Standard Cells
4.    Functional Blocks
5.    CMOS Logic

II.         Hardware Description Languages
1.    Verilog HDL
2.    System C
 
III.       ArchitectureDesign
1.    Datapath design
2.    Control logic
3.    Memory

IV.      Logic design
1.    Logic minimization
2.    Logic synthesis
3.    Logic simulation
V.         Circuit design
1.    Timing
2.    Power
3.    Noise

VI.      Layout design
1.    Placement
2.    Routing

VII.     Semiconductor manufacturing
1.    Fabrication overview
2.    Lithography process

VIII.   Packaging
1.    Package hierarchy
2.    Package design choices

IX.      Validation
1.    Design for testability
2.    Pre-silicon validation
3.    Silicon debug
4.    Prototype evaluation
Laboratory Sessions:
•         VLSI tools tutorial
•         HDL programming including Verilog or VHDL
•         Standard cell design
•         Layout design
•         Timing Analysis
•         Power Analysis
Textbook:
1.     N. H. E. Weste, and D. Harris: CMOS VLSI Design - A Circuits and Systems Perspective, Addison Wesley, 4th edition, 2010
Reference Books:
1.     M. John, S. Smith: Application-Specific Integrated Circuits, Addison-Wesley, 1997
2.   J. M. Rabaey, A. Chandrakasan and B. Nikolic:Digital Integrated Circuits – A Design Perspective , Prentice Hall, 2nd edition 2002
3.     W. Wolf:Modern VLSI Design – IP-based Design, Prentice Hall, 4th edition 2008
4.     J. Smith: HDL Chip Design : A Practical Guide for Designing, Synthesizing & Simulating ASICS & FPGAS Using VHDL or Verilog, Donne Publishing, 1996

Journals and Magazines:
1.     IEEE Transactions on VLSI Systems, IEEE
2.     IEEE Transactions on CAD of Integrated Circuits and Systems, IEEE
3.     IEEE Journal of Solid State Circuits, IEEE
4.     IEEE Transactions on Circuits and Systems, IEEE
5.     IEEE Transactions on Power Electronics, IEEE
6.     ACM Transactions on Design Automation on Electronic Systems, ACM
7.     Journal of VLSI Signal Processing, Kluwer
8.     Journal of Microprocessors and Microsystems,Elsevier
9.     Journal of Microelectronics, Elsevier
Time Distribution and Study Load:
•         Lectures: 30 hours
•         Laboratory sessions: 45 hours
•         Presentations: 3 hours
•         Self-study: 40 hours
•         Project: 50 hours
Teaching and Learning Methods:
This course combines a few learning channels. The lectures provide the students with the basic understanding of the subject. To increase understanding on the subject and become active learners, the students are required to do laboratory assignments, literature review, and presentation. The laboratory assignments strengthen their understanding and give them a chance to work in group. The literature review is the individual assignment. The presentation is a part of the individual assignment for personal development and knowledge sharing.
Evaluation Scheme:
The final grade will be computed according to the following components: midsemester exam 20%; final exam 30%; laboratories 10% and project 40%. Open-book examination is used.

An “A” would be awarded if a student can demonstrate clear understanding of the knowledge learned in class as well as from the laboratory assignments and literature reviews.

A “B” would be awarded if a student can understand the basic principles of the knowledge learned in class, from the laboratory assignments and from literature reviews.

A “C” would be given if a student can understand partially the basic principles of the knowledge learned in class, from the laboratory assignments and from literature reviews.

A “D” would be given if a student shows lack of understanding of the knowledge learned in class, from the laboratory assignments and from literature reviews.
Instructor(s):
SECTION NAME
A
B