School of Engineering and Technology, (SET)

AT81.08 : Advanced VLSI System Design  3(1-6)
Rationale:

This project-oriented course will consist of the specification, design, implementation, fabrication and testing of a large VLSI chip. Advanced CMOS design topics are covered including HW/SW co-design, high speed CMOS and low power design techniques. System level design entities such as data paths (e.g, ALUs, Register Files, Functional Units), memory, controllers, and clock and power distribution schemes. The high-level description language and high-level synthesis tools are also covered as well as Design-For-Testability design issues. Students work in groups of 2 persons to design, implement and test a CMOS implementation of a system level design entity such as a microcontroller, microprocessor, DSP.

Catalog Description:

Design tools for IC prototyping, Clock and signal distribution, Interconnect issues, IP based Design, Design for testability, Advanced topics in digital system design.

Pre-requisite(s):

None

Course Outline:
I.             Introduction to System-on-Chip design
1.      IP-based design
2.      FPGA based design
 
II.          Low power design
1.      Architecture level
2.      Circuit level
 
III.       Design for testability
1.      Test problems in digital systems
2.      Testing combinational and sequential logic
3.      Scan design
4.      Buit-in-Self-Test design
 
IV.       Formal verification
1.      Equivalence checking
2.      Model checking
 
V.          Fault simulation and test generation
1.      Fault simulation
2.      Advanced test generation
3.      Fault simulation
4.      Fault injection
 
VI.       Network-on-chip
3.      Network topology
4.      Routing mechanism
           
VII.    Gigascale-integration
1.      Fundamental limit
2.      Interconnect-centric architecture
3.      Noise and crosstalk for deep-submicron design 
Textbook:

W. Wolf: Modern VLSI Design: IP based design (4th Edition), Prentice Hall, 2008

References:
M. John, S. Smith:
Application-Specific Integrated Circuits, Addison-Wesley, 1997
 
J. M. Rabaey, A. Chandrakasan and B. Nikolic:
Digital Integrated Circuits – A Design Perspective , Prentice Hall, 2002
 
J. Smith:
HDL Chip Design : A Practical Guide for Designing, Synthesizing & Simulating ASICS & FPGAS Using VHDL or Verilog, Donne Publishing, 1996
 
A. Chandrakasan, R. Brodersen:
Low-power CMOS Design, IEEE press, 1998.
 
J. A. Davis, J. D. Meindl:
Interconnect Technology and Design for Gigascale Integration, Springer, 1st Edition, 2003.
Journals/Magazines/Websites:
IEEE Transactions on VLSI Systems
IEEE Transactions on CAD of Integrated Circuits and Systems
IEEE Journal of Solid State Circuits
IEEE Transactions on Circuits and Systems
IEEE Transactions on Power Electronics
ACM Transactions on Design Automation on Electronic Systems
Kluwer Journal of VLSI Signal Processing
Elselvier journal of Microprocessors and Microsystems
Elselvier Journal of Microelectronics
Grading System:
The Final grade will be computed according to the following components:
 
Midsem exam 20%
Final exam 20%
Assignments and laboratories 20% and
Project 40%.
 
Open-book examination is used for both mid-term and final exam.
Instructor(s):
SECTION NAME