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Dr. Mongkol Ekpanyapong
Position:	Associate Professor Department Head, ISE
Country of Origin:	Thailand

Email:

mongkol@ait.ac.th

Ext: 5689

URL:[Link to related/personal web page]

Academic Affiliation

Mechatronics
School of Engineering and Technology

Areas of Expertise (Keywords)

Computer architecture
VLSI design
Embedded Systems
Physical VLSI design
Compiler

Education

Georgia Institute of Technology, Atlanta, Georgia, USA Doctor of Philosophy in Electrical and Computer Engineering Ph.D. thesis: Microarchitecture-Aware Physical Planning for Deep Submicron Technology	2003- 2006
Georgia Institute of Technology, Atlanta, Georgia, USA Master of Science in Electrical and Computer Engineering	2001 - 2003
Asian Institute of Technology, Pathumthani, Thailand Master of Engineering in Computer Science Master’s thesis: FPGA-based video compression using OBDD representation	1998 - 2000
Chulalongkorn University, Bangkok, Thailand Bachelor of Engineering in Computer Engineering Senior project: R4000 hardware architecture design and implementation	1993 - 1997

Professional Experience

Assistant Professor, Asian Institute of Technology, Thailand	2009-present
Senior Computer Architect, Mobility Microprocessor Group, Intel Corporation, California, USA	2006-2009
Intern in Mobility Microprocessor Group, Intel Corporation, California, USA	Spring 2006
Intern in Physical Compiler Group, Synopsys Inc., Hillsboro, Oregon	Summer 2004
Graduate Research Assistant, Center of Research in Embedded Systems and Technology, Georgia Institute of Technology, Atlanta, Georgia, USA	2001 - 2004
Graduate Research Assistant, Internet Research Lab, Asian Institute of Technology, Thailand	1998 - 2001
Graduate Teaching Assistant, Asian Institute of Technology, Thailand	1999 - 2000
System Engineer, United Communication Network, Bangkok, Thailand	1997 - 1998
Intern in Hardware Design group, Submicron Corporation, Thailand	Summer 1996

Present Research Involvements

Research Interests

Physical VLSI Design

3D bus planning for microarchitecture-driven floorplanning
Implemented an algorithm for both dynamic and leakage power minimization using dual Vth/Vdd scaling and retiming
Developed a statistical timing analysis algorithm for sequential circuits to address process variations issue
Implemented an algorithm for thermal driven three dimensional (3D) microarchitecture-driven floorplanning that considers both performance and temperature during the floorplan design
Contributed to the development of the placement and routing algorithms for polymorphic computing architecture using integer linear programming and simulated annealing
Studied the design space exploration for microarchitecture-driven floorplanning using conjugated gradient search
Developed a net-weight scheme for Synopsys Physical Compiler
Developed an algorithm for microarchitecture-driven floorplanning using linear programming relaxation
Contributed to the development of 3D circuit placement to minimize wirelength and via using min-cut based placement
Implemented an extension of performance driven placement using retiming by using circuit characteristics to improve the net weight algorithm

Computer Architecture

Architected dynamic prefetch throttling technique for Intel next-generation Core architecture
Architected Instruction Scheduling framework for Intel next-generation graphics architecture
Studied cache, memory controller, and memory sub-systems for Intel next-generation Core architecture
Studied pixel shader schemes for Intel next-generation graphics processor
Analyzed and modeled microprocessor features for Intel Core 2 architecture (Penryn, world first 45nm microprocessor)
Validated post-silicon performance for Intel Core 2 architecture (Penryn)
Correlated RTL and simulator performance for Intel Core 2 architecture (Penryn)
Implemented a novel hybrid branch prediction scheme in SimpleScalar (RISC simulator) framework, which decreases the energy consumed by branch predictors.
Contributed to the development of HPL-PD (Trimaran) simulator for VLIW/EPIC machines to support cache
Enhanced the HPL-PD (Trimaran) simulator for VLIW/EPIC machines to generate assembly code and to improve runtime
Contributed to the Implemented an extension of SimpleScalar to support non-uniform latency data forwarding

VLSI Design

Studied the impact of custom design for Intel next-generation graphics processor
Designed, implemented, and validated radix-16 divider as a part of Clipper unit for Intel next-generation graphics processor
Designed and implemented RTL for a Front-end subsystem for Intel Core 2 architecture (Penryn)
Designed OBDD-based video compression circuit
Designed and implemented a R4000 processor
Designed and implemented a Neural network circuit (feed forward part)

Compiler

Contributed to the development of a novel data prefetching algorithm (load dependence graph) that uses available resources on VLIW/EPIC machine
Contributed to the development of a hybrid register allocation algorithm (profile based + linear scan)
Implemented a weighting scheme for Trimaran instruction scheduler

Doctoral Research Supervision

Selected Publications

M. Ekpanyapong, K. Kanchanasut, and C. Lursinsup, Design of FPGA-based video compression using OBDD, in International Symposium on Communications and Information Technologies (ISCIT) 2001.
M. Ekpanyapong and S. K. Lim, Performance-driven global placement via adaptive network characterization, in ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC) 2004.
M. Ekpanyapong, K. Balakrishnan, V. Nanda, and S. K. Lim, Simultaneous delay and power optimization for multi-level partitioning and floorplanning with retiming, in IEEE International Symposium on Circuits and Systems (ISCAS) 2004.
M. Ekpanyapong, J. Minz, T. Watewai, H-H. S. Lee, and S. K. Lim, Profiling-guided microarchitectural floorplanning for deep submicron processor design, in ACM Design Automation Conference (DAC) 2004.
R. M. Rabbah, H. Sandanagobalane, M. Ekpanyapong, and W. F. Wong, Compiler-orchestrated prefetching via speculation and predication, in Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2004.
M. Ekpanyapong, P. Korkmaz, and H-H. S. Lee, Choice predictor for free, in Asia-Pacific Computer Systems Architecture Conference (ACSAC) 2004.
M. Ekpanyapong, M. Healy, and S. K. Lim, Placement for Configurable Dataflow Architecture, in ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC) 2005.
M. Ekpanyapong, S. K. Lim, C. Ballapuram, and H-H. S. Lee, Wire-driven Microarchitectural Design Space Exploration, in International Symposium, in Circuits and Systems (ISCAS) 2005.
M. Healy, M. Ekpanyapong, and S. K. Lim,Placement and Routing for Configurable Dataflow Architecture, in International Conference on Field Programmable Logic and Application (FPL) 2005.
M. Ekpanyapong, T. Watewai, and S. K. Lim, Statistical Bellman-Ford Algorithm with an Application to Statistical Retiming, in ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC) 2006.
M. Ekpanyapong, J. Minz, T. Watewai, H-H. S. Lee, and S. K. Lim,Profiling-guided microarchitectural floorplanning for deep submicron processor design, in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) 2006.
M. Healy, M. Vittes, M. Ekpanyapong, C. Ballapuram, S. K. Lim, H-H. S. Lee, and G. Loh, Microarchitectural Floorplanning under Performance and Temperature Tradeoff, in Design Automation and Test in Europe (DATE) 2006.
M. Ekpanyapong, M. Healy, and S. K. Lim, Profile-driven Instruction Mapping for Dataflow Architectures, in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) 2006.
M. Ekpanyapong and S. K. Lim, Retiming for Dual Supply and Threshold Voltage VLSI Circuits, in International Symposium on Physical Design (ISPD) 2006.
M. Healy, M. Vittes, M. Ekpanyapong, S. K. Lim, H-H. S. Lee, and G. Loh, Multi-Objective Microarchitectural Floorplanning for 2D and 3D ICs, in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD) 2007.
A. Nisar, M. Ekpanyapong, A. Valles, and K. Sivakumar, 45nm Core 2 Silicon Performance, Intel Technology Journal (ITJ) to be published august 2008.

Memberships/Credentials

Other

Served as a session Chair, Asia and South Pacific Design Automation Conference (ASPDAC) 2006
Presented at the Special Interest Group in Design Automation (SIGDA) University Booth as Georgia Institute of Technology representative (held together with Design Automation Conference) in 2003 and 2004
Served as a Compiler Architecture and Synthesis for Embedded Systems (CASES) 2003 and CASES 2004 conference web chair
Implemented a virtual web-based course on demand system and its authoring tool at istributed Education Center, AIT
Contributed to the development Web application for Information Retrieval for National Economic and Social Committee Institute of Thailand
Developed an application for online budget management for UNESCO Thailand
Participated in Micromouse competition as the Chulalongkorn University representative

AWARDS

Award in hardware design contest, Nectec, Thailand, 1997
ISPD best paper candidate 2006

PATENTS

P. J. Smith, M. Ekpanyapong, H. Baliga, and I. Kim, Tracking temporal use associated with cache evictions (under submission)